The present invention relates to a system and method for reading nonvolatile memory, and more particularly, to a system and method for reading nonvolatile memory at power up.
In an integrated circuit memory chip or a system using nonvolatile memory, some of the defect locations may be replaced with the redundant memory. Some information stored in nonvolatile memory is recalled prior to any operation. The redundancy can be stored in a register after power-up by recalling from a nonvolatile memory space. The power typically is at a stable predetermined voltage level before reads are performed. Conventional systems wait a predetermined time after power-up before recalling data from the nonvolatile memory to ensure proper reading.
The present invention provides a method for recalling data from a memory including said method embedded therein and such memory. The method may not wait a predetermined time after initiation, power reset or power up.
The present invention provides a method that reads data stored in a first location of a memory in response to or after an initiation signal, compares the read data and a predefined data pattern to determine whether there is a match, and repeats the reading and comparing in the event that said comparing determines consecutive matches less than a predetermined maximum number of matches. The method may further comprise providing an indication of valid power after said comparing determines consecutive matches equal to a predetermined maximum count. The method may further comprise reading data stored in a second location of the memory, and may further comprise such reading in the event said comparing determines consecutive matches equal to the predetermined maximum number of matches.
The method may further comprise reading data stored in a second location of the memory in the event said comparing determines consecutive matches equal to the predetermined maximum number of matches, and repeating the reading data stored in a first location, the comparing, and the reading data stored in a second location a predetermined number of times.
The present invention provides a memory device comprising a memory, a register, a comparator, and a counter. The register stores a predefined data pattern. The comparator commands a read from the memory and the register and generates a match signal indicating a match in the event the data read from a first location of the memory matches the predefined data pattern and indicating a non-match in the event the data read from the first location does not match the predefined data pattern in response to an initiation signal. The counter causes the comparator to command a read and generate the match signal in the event that the match signal does not indicate a match for predetermined number of consecutive reads.